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QuickLogic Corporation

1277 Orleans Drive
Sunnyvale, CA 94089
USA
WebSite: http://www.quicklogic.com
Phone: 408-990-4000
Fax: 408-990-4040
Email: info@quicklogic.com
   

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Recent Articles for QuickLogic Corporation:
Increasing viewability, not backlighting, for displays
As display sizes on mobile phones and other consumer devices have grown, the importance of power consumption and display . . .
Increasing viewability, not backlighting, for displays
As display sizes on mobile phones and other consumer devices have grown, the importance of power consumption and display . . .
Product Roundup: Audio/video multimedia ICs
Consumers now demand a more compelling video content experience, better audio quality, and the ability to stream content and . . .
IP speeds application processor data transfer
The Smart Programmable Intelligent Data Aggregator (SPIDA) IP package creates an optimized link between peripheral I/O, such as USB . . .
Small-footprint SPI controller IP is fast
The Serial Peripheral Interconnect (SPI) host controller IP for customer-specific standard product ICs provides a fast, easy connection to . . .

Reference Design Documents for QuickLogic Corporation:
PCI 484 Reference Design Kit
The PCI-484 RDK is a development and demonstration board, supporting the QuickLogic 0.18 µm QuickPCI family of devices in a 484-pin BGA package. It is an open platform with a flexible (32/64-bit and 33/66 MHz support) PCI bus system connection. The PCI-484 RDK board is designed to work in the +3.3V PCI signaling environment.
EclipsePlus Reference Design Board
The EclipsePlus™ RDK can be used as a sales support demonstration system as well as a test bench for the QL7180 device.
Low Power Reference Design Board
The uWatt Low Power RDK has been created to provide a hardware platform for developing designs using QuickLogics uWatt Eclipse II FPGA family.
CS3311QL Convolutional Encoder
This Convolutional Encoder is a high performance implementation suitable for a range of Forward Error Correction applications. It may be used in conjunction with other FEC related cores available from ISS to rapidly construct complete FEC solutions. It has been developed in HDL and may be ported across a range of technologies and processes.
Utopia Level 2 Slave to Utopia Level 1 Master Multiplexer
The Utopia (Universal Test & Operations PHY Interface for ATM) interface is defined by the ATM Forum to provide a standard interface between ATM devices and ATM PHY or SAR (segmentation and Re-assembly) devices.The L2 Slave to L1 Master Multiplexer implements the necessary interfaces enabling to connect multiple Level 1 PHY devices to a Level 2 topology. The Multiplexer itself implements two or more Ports and aggregates them on the Level 2 interface.