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National Semiconductor

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ARROW ELECTRONICS FUTURE ELECTRONICS
AVNET ELECTRONICS MARKETING NEWARK
DIGI-KEY CORPORATION


RD-179 - High-IF Sub-sampling Receiver Subsystem Reference Design Kit
The SP16160CH1RB demonstrates a high-IF sampling receiver subsystem that provides signal amplification, digitization and clocking as used in wireless infrastructure systems. The subsystem includes the ADC16DV160 analog-to-digital converter (ADC), LMH6517 Digitally-controlled Variable-Gain Amplifier (DVGA) and LMK04031B precision clock conditioner. The subsystem addresses multi-carrier, multi-standard wireless basestations addressing GSM/EDGE, WCDMA, LTE and WiMAX standards. The SP16160CH1RB delivers an IF chain receiver sensitivity of -105 dBm, with a 9 dB carrier-to-noise ratio in a 200 kHz channel, at 192 MHz input IF. With the digitally-controlled variable gain amplifier (DVGA) set at a maximum gain of 22 dB, the sensitivity is limited primarily by the noise contribution of the DVGA. In the presence of a strong blocker, with the DVGA gain set at 12 dB and blocker level kept at 1.6 dBm input to the ADC, the SP16160CH1RB board delivers sensitivity of -86 dBm. In this blocking condition, the receiver sensitivity is determined by the ADC?s high spurious-free dynamic range (SFDR). In the signal path, the subsystem provides impedance-matched, single-to-differential conversion through a 1:4 transformer and a 31.5 dB amplification gain range in 0.5 dB steps through the DVGA. The anti-aliasing filter at the output of the DVGA provides noise filtering and over 40 dB harmonic suppression by selecting the 20 MHz signal band centered at 192 Hz. The signal is then sampled and quantized by the ADC into 16-bit words using a 153.6 MHz CMOS clock. In the clock path, a LMK04031B clock conditioning circuit operates with a 61.44 MHz reference oscillator and 76.8 Hz VCXO to provide the 153.6 MHz CMOS sampling clock. The clock output is also filtered and buffered to provide very low broadband noise for less than 200 fs total jitter over the clock input bandwidth of the ADC. To simplify evaluation of the SP16160CH1RB, National offers the WaveVision 5.1 data capture board
High-Performance Video Clock Module for Xilinx Virtex-5 LXT FPGAs
National's ML571-1982CLK clock module plugs into a Xilinx Virtex-5 development platform to create a complete video timing reference design for triple-rate (3G/HD/SD) SDI applications.
SDI/SDV Evaluation Boards
SDI evaluation boards are available for a nominal charge that demonstrate the basic operation of the SDI/SDH/SDV devices. The evaluation boards can be ordered through National's Distributors. The table provides Product Family, PCB Description, NSID of devices on the PCB, and the evaluation board order number.
Triple-rate SDI & Video Clocking Daughter Card for Xilinx Spartan-3A/3E FPGAs
National Semiconductor in collaboration with Avnet and Xilinx developed a triple-rate SDI and video clocking daughter card for the Xilinx Spartan-3A/3E development kits. The combined solution provides broadcast video system designers a comprehensive platform for rapid evaluation and prototyping of new designs to reduce time to market. The 3G SDI SerDes evaluation system consists of Xilinx XtremeDSP starter platform Spartan-3A DSP 1800A edition (sold separately by Xilinx), National's SDI video and clocking daughter card (SDXILEVK), SDXILEVK Schematics, Bill of Materials (BOM)and FPGA IP.
Triple-rate SDI & Video Clocking Daughter Card for Altera Cyclone III FPGAs
National Semiconductor in collaboration with Altera developed a triple-rate SDI and video clocking daughter card for the Altera Cyclone III development kit. The combined solution provides broadcast video system designers a comprehensive platform for rapid evaluation and prototyping of new designs to reduce time to market. The 3G SDI SerDes evaluation system consists of: Cyclone III FPGA development board (sold separately by Altera, National's SDI video and clocking daughter card, comprehensive user manual, schematics, and bill of materials (BOM).
eeTechBriefs – 15-Minute on-demand multimedia web casts covering the latest product developments.

The IEEE 1588 precision time protocol (PTP) allows designers to synchronize slave clocks to a master clock over Ethernet. By using the same time base for all events and timestamps, networked devices can be synchronized with exceptional precision. The DP83640 Precision PHYTER® device from National Semiconductor delivers the highest level of precision clock synchronization for real time industrial connectivity based on the IEEE 1588 standard.

View this brief Webcast to learn more about the following design topics:

• What is the IEEE 1588 PTP and how does it synchronize a network?
• Network topology, time adjustments and rate correction
• Adding PTP synchronization to a system
• Implementation options and considerations
• DP83640 precision PHYTER features and benefits

By attending this event, you’ll learn how the 1588 PTP fits into the Ethernet standard and how you can achieve new levels of precision in your next application without increasing development or total system costs.


Are you constantly looking for ways to simplify the design process and get new designs optimized and to market faster? If so, National Semiconductor can help. National is introducing 2 new SIMPLE SWITCHER® families complemented by a robust set of design and optimization tools.

Join National Semiconductor’s Courtney Burry for a 12-minute Webcast discussing:

• The New WEBENCH® Power Designer
• LM315x Synchronous SIMPLE SWITCHER® Controller Series
• LM2267x and LM22680 SIMPLE SWITCHER® Regulator Series
• Additional design support and tools

In less than 12 minutes, you'll gain an understanding of how to design flexible power supply solutions without compromising ease-of-use or reliability. Also, Webcast viewers will be eligible to win free evaluation boards. You’ll need to act fast though as quantities are limited!


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