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Lattice Semiconductor Corp.

5555 N.E. Moore Ct.
Hillsboro, OR 97124
USA
WebSite: http://www.latticesemi.com
Phone: 503-681-0118
Toll Free: 800-FASTGAL
Fax: 503-681-3037
Email: sales@latticesemi.com
   

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Recent Articles for Lattice Semiconductor Corp.:
Update refines Diamond FPGA design tool
Version 2.0 of Diamond design software for Lattice FPGAs adds support for ECP4 devices, aids rapid design timing closure, . . .
LatticeECP3 FPGA family expanded
The LatticeECP3 family of FPGAs has new versions with small package size, lower power, and higher speed. The low-power . . .
Using FPGAs for camera sensor interfaces
The image sensor is arguably the most important component in a digital video or still camera. But these sensors . . .
Lattice Semiconductor To Acquire Siliconblue
Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced it has entered into a definitive agreement to acquire SiliconBlue Technologies, a . . .
Power-efficient communication engines in FPGAs
The rapid pace of innovation across industries is driving new approaches to electronic system design. Designers are increasingly seeking . . .

Reference Design Documents for Lattice Semiconductor Corp.:
LATTICE RELEASES REFERENCE DESIGN FOR GPON BURST MODE RECEIVER
Lattice Semiconductor Corporation announced the availability of its PURESPEED™ I/O Burst Mode Receiver (BMR) FPGA Reference Design for Gigabit Passive Optical Networks (GPON). This reference design uses Lattice's unique Adaptive Input Logic (AIL) block found on its LatticeSC™ FPGAs and LatticeSCM™ FPGAs (collectively, the LatticeSC/M family) to rapidly establish stable clock to data timing relationships within the fast lock times specified in the GPON ITU-T G.984.1 specification, which requires the Optical Line Termination (OLT) to lock to incoming data within 50 bit times.
Telecom Bus Bridge for SONET Cross Connect
The Telecom Bus Interface (TBI) is an accepted industry standard that is commonly found in SONET/SDH systems. It is a parallel interface used for chip-to-chip communication on SONET line cards.
LATTICE RELEASES REFERENCE DESIGN FOR GPON BURST MODE RECEIVER
Lattice Semiconductor Corporation announced the availability of its PURESPEED I/O Burst Mode Receiver (BMR) FPGA Reference Design for Gigabit Passive Optical Networks (GPON). This reference design uses Lattice's unique Adaptive Input Logic (AI
Multiple Boundary Scan Port Addressable Buffer
The LSC BSCAN-1 is a multiple boundary scan test access port (TAP) addressable buffer function that can be accessed through a standard IEEE 1149.1 interface. With three Local Scan Ports (LSP), the BSCAN-1 function can be structured as hierarchical ports with the ability to add and remove local scan chains to improve test throughput.
Multiple Boundary Scan Port Linker
According to the IEEE 1149.1 Boundary Scan System, every complex system can have more than one boundary-scan-compliant scan port. If each of these scan ports are linked together, then the chances of enhancing the scan capability would definitely increase. In this design, the multiple scan ports are linked together by implementing instructions feed in to the IEEE 1149.1 port.