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Altera Corporation

101 Innovation Drive
San Jose, CA 95134
Phone: 408-544-7000
Fax: 408-544-6401

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Recent Articles for Altera Corporation:
Design suite handles ARM CPU, Altera FPGA
The Altera SoC Embedded Design Suite now includes the ARM DS-5 Altera Edition toolkit for SoCs and features FPGA-adaptive . . .
FPGA IP available for 40/100 GbE
The 40-Gbit/s and 100-Gbit/s Ethernet intellectual property (IP) cores are effective tools for building systems requiring very high throughput-rate . . .
Quartus FPGA design software adds features
Quartus II PLD/FPGA design software version 11.1 provides expanded support for Altera’s 28-nm FPGAs, including Stratix V, Arria V, . . .
28-nm FPGAs add fast I/O, cut dynamic power
The Cyclone V and Arria V 28-nm FPGA families are said to provide a 50% dynamic power reduction, compared . . .
Low-power CPLDs have 40 to 2,210 LEs
The low-power MAX V CPLD family has from 40 to 2,210 logic elements and features static power as low . . .

Videos for Altera Corporation:
Altera looks at FPGA Verification and Prototyping
FPGA's have become as complex at Gate Arrays and verification of FPGA-based systems has become just as difficult and time consuming as their standardized cousins.
FPGA's have become as complex at Gate Arrays and verification of FPGA-based systems has become just as difficult and time consuming as their standardized cousins. Every year, there are new companies that claim to make that verification process simple and effective, but are they right? Do all verification roads lead to the same place? Footwasher Media Editorial Director Lou Covey sat down with Altera's Phil Simpson, senior manager for software product planning, and looked at the state of the market and technology.
Altera NIOSII Development Demo
Altera Booth at ESC
Murray Slovick Talks with Altera about the NIOSII Development Kit with Bob Garrett
Reference Design Documents for Altera Corporation:
Avalon State Sequencer Reference Design
The Altera® State Sequencer is a small-footprint SOPC Builder component that provides functionality for fast switching of a large number of signals external to the Avalon™ system in a completely deterministic manner, with zero-latency response to inputs.
Avalon MicroSequencer Reference Design
The Altera Avalon MicroSequencer is a high-speed, low logic element (LE)-usage Avalon master with 32-bit data and address buses that employs a minimal instruction set to perform Avalon bus transfers as well as simple calculations. It can be used to control, initialize, and service peripherals in an Avalon system in applications that require extremely deterministic behavior.
Video and Image Processing Example Design
The Altera® Video and Image Processing (VIP) Example Design demonstrates dynamic scaling and clipping of a standard definition video stream in either National Television System Committee (NTSC) or phase alternation line (PAL) format and picture-in-picture mixing with a background layer. The video stream is output in high definition resolution (1024×768) over a digital video interface (DVI).
Triple Speed Ethernet Data Path Reference Design
The Altera® Triple Speed Ethernet (TSE) data path reference design provides a sample SOPC Builder system using the Altera TSE MegaCore® function with two serial transceivers. This reference design demonstrates the operation of the Altera TSE MegaCore function up to the maximum wire-speed performance in hardware. The design enables you to evaluate the TSE MegaCore function for integration into Altera FPGA designs.
Serial Digital Interface Demonstration
The serial digital interface (SDI) demonstration for the Stratix® II GX video development board uses two instances of the Altera® SDI MegaCore® function. The Stratix II GX video development board is part of the Audio Video Development Kit, Stratix II GX Edition.